High-Speed High-Resolution CT ΔΣ ADC

Chip Details

A high-speed (BW = 150MHz) high-resolution (>12 bit) CT ΔΣ ADC is designed in 28 nm CMOS. Design challenges:

1. DAC mismatch (degraded SFDR);

2. OPAMP insufficient GBW (degraded SNR);

3. Low supply voltage (core VDD = 0.85 V)