University of Arizona
Department of Electrical and Computer Engineering
ECE 274A: Digital Logic
Textbook and Materials    Course Outline    Course Organization    Grading   General Policies   Labs
Time: Monday, Wednesday, Friday 10:00pm - 10:50am
Location: C. E. Chavez Bldg, Rm 111
Instructor: Tosiron Adegbija, Email: firstname.lastname@example.org
Office: 356C; Office hours: Mondays, Wednesdays 11am - 12noon, or by appointment
Mohammed Attia, Email: email@example.com, Office Hours: TBA
Keeley Criswell, Email: firstname.lastname@example.org, Office Hours: TBA
The course schedule will be updated on this website, while homework, reading assignments, project description, etc. will be posted on D2L
In this class, we will cover the fundamental principles underlying the arrangements of elements in a computer or digital device so as to perform a specific task. You will learn how to design and implement basic building blocks of a digital system. You will then learn how to put together these pieces to construct digital components of larger systems such as a medical device, automobile, cell phone, home security system, robot, and many other systems. This class will involve a lot of work, but will be pivotal for your future career as an engineer. Hopefully, you will also have a lot of fun learning in this class! :)
Programming in C/C++
Textbook and Materials
1. Sign up at zyBooks.com (only 'arizona.edu' emails are allowed)
2. Enter zyBook code: ArizonaECE274ASpring2016
3. Click 'Subscribe'
The following books are recommended if you choose to have additional resources:
- Digital Design, 2nd edition, Frank Vahid, John Wiley and Sons
- Digital Design and Computer Architecture, David Harris, Sarah Harris, Morgan Kaufmann
- Contemporary Logic Design, Randy H. Katz, Gaetano Borriello, Prentice Hall
- Verilog for Digital Design, Frank Vahid, Roman Lysecky, John Wiley and Sons
- Boolean Algebra
- Combinational Logic, Common Combinational Components
- Basic Storage Elements
- Controllers, Sequential Logic Design Process
- Multifunction Registers, Adders, Incrementers, Comparators, Multipliers
- Subtractors, Signed Numbers, ALUs, Shifters, Counters, Timers, Register Files
- RTL Design
- Combinational Optimization, Sequential Optimizations
- Datapath Component Tradeoffs
- Physical Implementation, FPGA Overview
- Course involves class (3 credits) and laboratory (1 credit) activities.
- Reading assignments are due at 9.30am before the class starts (almost every lecture session)
- Class activities will involve assignments, announced/pop in-class quizzes, design challenges, 4 examinations and a comprehensive final exam.
- Participation on Piazza will constitute extra credit (up to 1% of final grade)
After each lecture, a reading assignment will be given. Each reading assignment from the online book will involve participation exercises. Completing these exercises before the next class will be mandatory. Those exercises will be graded as your assignments. Weight of a participation assignment will be in the range of 2-10 points based on the amount of workload required by that assignment. Your progress in reading and participation exercises as of 9:30am on the due date will be used for grading by me and TAs online. There is no formal assignment submission.
- 40% - Exams (4 total)
- 20% - Comprehensive final exam
- 25% - Lab assignments (6-8 total) and Lab Practical (4 total)
- 15% - Reading and participation exercises (7%), In-class quizzes (8%)
- 90 - 100%: A
- 80 - 89%: B
- 70 - 79%: C
- 60 - 69%: D
- NO LATE ASSIGNMENTS WILL BE ACCEPTED, except under extreme non-academic circumstances discussed with me at least three days before the assignment is due.
- Make-ups for assignments and exams may be arranged if a student's absence is caused by documented illness or personal emergency. A written explanation (including supporting documentation) must be submitted to me. If the explanation is acceptable, an alternative to the graded activity will be arranged.
- Regrade requests must be submitted in writing within three days after the grades have been received/posted.
- Any extenuating circumstances that have an impact on your participation in the course should be discussed with me as soon as those circumstances are known.
- Inquiries about graded material must be turned in within 3 days of receiving a grade.
- I reserve the right to modify course policies, course calendar, assignment values and due dates, as circumstances require.
- You are strongly encouraged to attend the classes. In general, I have found that positive learning outcomes and good grades are highly correlated with consistent class attendance and in-person interactions with instructors during class/office hours. Also, there will be material covered in class that may not be on the slides or in the textbook. Lecture notes are intended to serve as a supplement and not as a substitute for attending class.
- You are encouraged to discuss the assignment specifications with me, your teaching assistants, and your fellow students. However, anything you submit for grading must be unique and should NOT be a duplicate of another source. The Department of Electrical and Computer Engineering expects all students to adhere to UofA's policies and procedures on Code of Academic Integrity.
Cell Phones and Electronics
Please remember to turn your phones to silent or off during lecture. Use of cell-phones during class is strictly prohibited. You may only use laptops/tablets to support in-class activities (e.g., viewing current class slides). If I find them to be distracting, they will be completely disallowed.
Communication with the Instructor
Questions on materials discussed in class should be posted on Piazza, so that the whole class can contribute and/or learn from the discussions/answers. However, you may email me with personal questions, logistics, etc. When sending emails to me, please remember that many students may have the same name. So please use your full name, and be as specific as you can (list the course, section, etc. -- whatever is relevant to your communication). Please try to be professional and use reasonable grammar and formatting. Also, please include the course number in brackets in your subject (i.e. [ECE 274A]) so that I can sort my email.
Laboratory involves hands-on and coordinated sequence of activities in which, students incrementally design, develop and test components using modern synthesis tools and FPGA prototyping boards. Students leave the class with a complete understanding of digital design from theory to practice, and with industry-relevant skills in design, development, debugging and testing. Laboratory activities will accompany the topics covered in the lectures with hands on programming based assignments. Please note that you may need to work outside of the lab section to complete all of your assignments.
A lab assignment may have a pre-lab (checked by TA at the beginning of lab session) and code-check (at the end of lab session). You must additionally submit your Verilog files for each lab assignment to the designated D2L dropbox on the day the lab assignment is due. Note, the code submitted on D2L should be the same code demoed in lab. Students must work in a group of two. Graduate students are required to work on an individual basis.
In addition, students will complete a lab practical on an individual basis. Students will be provided with a short problem statement and have 75 minutes to design, test, and submit their solution and the accompanying testbench in the designated D2L drop box.
Students requesting classroom accommodation must register with the Disability Resource Center for assistance with obtaining the necessary accomodations, and request the DRC to send me official notification of your accommodation needs as soon as possible. Please plan to meet with me to discuss accommodations and how to maximize your productivity in this class.
Additionally, resources are available on-campus for students having personal problems or lacking clear career and academic goals. Students who need assistance should contact Counseling and Psych Services for the necessary assistance.