Downloads

To enable reproducibility of our research, this page contains research artifacts, including data, workloads, and any modified simulators used in our research, along with the associated references.

Energy Characterization of Graph Workloads

Click here to download the data generated and used in our SUSCOM paper:

• Energy Characterization of Graph Workloads
  Ankur Limaye, Antonino Tumeo, and Tosiron Adegbija
  ELSEVIER Sustainable Computing (SUSCOM)/IEEE International Green and Sustainable Computing Conference (IGSCC20-Journal-Integrated Issue), October 2020.
  [PDF] [URL]

Prefetching for Reduced Retention STTRAM Caches

Click here to download the modified version of GEM5 used for the STTRAM cache prefetching study described in our ICCD paper:

• A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches
  Kyle Kuan and Tosiron Adegbija
  IEEE International Conference on Computer Design (ICCD), October 2020.
  [PDF]

ECG-based Authentication using Timing-Aware Domain-Specific Architecture

Click here to download the ECG code used in our CODES/TCAD paper:

• ECG-based Authentication using Timing-Aware Domain-Specific Architecture
  Renato Cordeiro, Dhruv Gajaria, Ankur Limaye, Tosiron Adegbija, Nima Karimian, and Fatemeh Tehranipoor
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)/CODES+ISSS, September 2020
  [PDF] [URL]

SCART: Predicting STT-RAM Cache Retention Time Using Machine Learning

Click here to download the data used in our IGSCC paper:

• SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning
  Dhruv Gajaria, Kyle Kuan, and Tosiron Adegbija
  International Green and Sustainable Computing Conference (IGSC), Washington DC, October 2019
  [PDF]

ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors

Click here to download the data used in our MEMSYS paper:

• ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors
  Dhruv Gajaria and Tosiron Adegbija
  International Symposium on Memory Systems (MEMSYS), Washington DC, USA, October 2019
  [PDF]

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems

Click here to download a modified version of GEM5 that implements different shared L2 cache retention time banks as described in our IEEE Transactions on Computers (TC) paper:

• HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems
  Kyle Kuan and Tosiron Adegbija
  IEEE Transactions on Computers (TC)
  [PDF] [URL]

Benchmarks and Workload Characterization for the Internet of Medical Things

Click here to download the HERMIT benchmarks for the Internet of Medical Things (IoMT). Each directory contains README files on how to compile and run the workloads.

Please refer to and cite the following papers for details on the workloads and their characteristics:

• HERMIT: A Benchmark Suite for the Internet of Medical Things
  Ankur Limaye and Tosiron Adegbija
  IEEE Internet of Things Journal, 2018.
  [PDF]

• A Workload Characterization for the Internet of Medical Things (IoMT)
  Ankur Limaye and Tosiron Adegbija
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, July 2017
  [PDF]

LARS: Logically Adaptable Retention Time STT-RAM L1 Cache

Click here to download a modified version of GEM5 that implements different cache retention times as described in our DATE and TCAD papers:

• Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design
  Kyle Kuan and Tosiron Adegbija
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  [URL] [PDF]

• LARS: Logically Adaptable Retention Time STT-RAM Cache for Embedded Systems
  Kyle Kuan and Tosiron Adegbija
  Design, Automation and Test in Europe (DATE), Dresden, Germany, March 2018.
  [PDF]