Past Research |
Asynchronous VLSI Adaptive Echo Cancellation
Student: Richard P. Mackey
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An asynchronous, single-chip, high-speed communication adaptive echo canceller
was designed in this project. Adaptation is based on the LMS algorithm
with power-of-two convergence factor. Cancellation is performed by a 128-coefficient
adaptive finite impulse response filter whose coefficients are updated
every cycle. The LMS power-of-two update equations were modified to allow
a pipelined implementation. Pipelining the adaptation and echo estimation
operations enabled hardware minimization, a high sampling rate, and no increase
in convergence time. The resulting circuit updates the filter coefficients and
generates the output at a sampling rate greater than 205 kHz. The chip was
designed using 0.8-micron CMOS standard cells. The single-chip layout requires
a die size of 9.25 mm by 7.25 mm.
Publications:
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Richard P. Mackey, Jeffrey J. Rodriguez, Jo D. Carothers and
Sarma B. K.
Vrudhula, "Asynchronous VLSI Architecture for Adaptive Echo
Cancellation," Electronics Letters, vol. 32, no. 8,
April 11, 1996, pp. 710-711. [ PDF ]
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Richard P. Mackey, Jeffrey J. Rodriguez, and Jo Dale
Carothers, and Sarma B. K. Vrudhula,
"A Single-Chip, Asynchronous
Echo Canceller for High-Speed Data Communication," in Proc.
Eighth Annual IEEE Intl. Application Specific Integrated Circuit Conf.
and Exhibit, Austin, Texas, Sept. 18-22, 1995, pp. 181-184. [ PDF ]
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