ECE274 Digital Logic - Fall 2005

Course Information

Instructor:

Roman Lysecky (rlysecky@ece.arizona.edu)
Office Hours: MW 1:00-2:00PM or by appointment.
Office: ECE 320F

Lecture:

MWF 12:00-12:50PM, ILC 140

Lab:

Section 1:  M 2:00PM-4:50PM,  ECE 301,  TA: Annapoorna Krishnaswamy
Section 2:  T 8:00AM-10:50AM,  ECE 301,  TA: Julian Sosa
Section 3:  T 2:00PM-4:50PM,  ECE 301,  TA: Julian Sosa
Section 4:  W 2:00PM-4:50PM,  ECE 301,  TA: Annapoorna Krishnaswamy
Section 5:  T 11:00AM-1:50PM,  ECE 301,  TA: Haiyong Zhang
Section 6:  R 11:00AM-1:50PM,  ECE 301,  TA: Haiyong Zhang
Section 7:  R 2:00PM-4:50PM,  ECE 301,  TA: Julian Sosa
Section 8:  F 2:00PM-4:50PM,  ECE 301,  TA: Annapoorna Krishnaswamy

Teaching Assistants

Haiyong Zhang, (hzhang@email.arizona.edu)
Julian Sosa, (jsosamol@email.arizona.edu)
Annapoorna Krishnaswamy, (annakris@email.arizona.edu)

Textbooks:

Fundamentals of Digital Logic with Verilog Design, Stephen Brown, Zvonko Vranesic, McGraw-Hill
McGraw-Hill's Book Website

Digital Design, Frank Vahid, John Wiley and Sons
Frank Vahid's Book Website
John Wiley and Sons' Book Website

Grading:

Grading for the class will be performed on an individual basis. You will not be competing with the other students for your grade. If all students do well in the class, it is possible everyone will get an A. Your grade is only dependent on the effort you put into the class. Letter grades will be assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B, 70% and above to a C, 60% and above to a D, and less than 60% to an E.

The grading will be based on a weighted sum as follows:

25%  Final
40%  Midterms
5%  Quizzes
10%  Homework Assignments
20%  Lab Assignments

Overall Educational Goals:

To introduce the fundamental theory behind the methods for designing and optimizing digital systems, to provide students with laboratory experience and basic competence in design using Hardware Description Languages (HDL), and to provide the necessary prerequisite background for subsequent courses in computer architecture, microprocessor programming and design, embedded systems design, and computer aided VLSI design.

Specific subjects to be covered include:

Students completing this course should have a good understanding of the concept of Boolean functions and their representations, including the concepts of canonicity and efficiency, the concept of optimal implementation, and delays in circuits. They are expected to able to take an informal specification of a combinational circuit function and synthesize an minimal gate two level implementation.

They are expected to have a basic understanding of sequential functions and be able to design an optimal synchronous finite state machine from an informal description. In addition, they are expected to know how to design basic system components such as multiplexors, decoders, adders, multipliers, flip flops, registers and counters. Students are expected to have an understanding of the importance of temporal behavior of digital circuits.

Students and expected to have a basic understanding of the register-transfer level (RTL) design methodology and high-level state machines. They are expected to know how to design a circuit using as a high-level state machine and convert that state machine to digital circuit implementation. Verilog design of digital circuits will be integrated throughout the course.

Specific Educational Outcomes:

Students completing the course should be able to:

  1. Give a precise definitions of a Boolean algebra, Boolean functions, implicants and prime implicants, and the SOP and POS canonical forms of representation.
  2. Know how to construct basic gates (inverter, AND and OR) using NMOS and PMOS switches.
  3. Know the cause of delays associated with logic gates.
  4. Know number representations in different bases, and methods for converting from one base to another.
  5. Know the different binary representations of signed integers (2s complement, 1s complement, sign magnitude), methods of conversion, and basic arithmetic operations (addition, subtraction, multiplication, division).
  6. Use Karnaugh maps and Quine-McCluskey tabular minimization technique for identifying all the prime implicants, and solve the covering problem to find a minimal gate, two-level implementation, for both completely specified and incompletely specified logic functions.
  7. Understand the principles behind the heuristic methods for two level logic minimization.
  8. Construct logic circuits of basic components such as adders, multipliers, decoders, multiplexors, etc.
  9. Have an understanding of programmable devices such as FPGAs, and know how to use them to implement digital circuits.
  10. Have an understanding of concept of state in functions that have history dependence.
  11. Understand the structure and operation of basic flip flops and latches.
  12. Know the structure and operation of ROMs and RAMs.
  13. Define a finite state machine and know what functions can and cannot be described as finite state machines.
  14. Be able to precisely define a Mealy and Moore machine, and transform one to the other.
  15. Know how to construct a tabular and graph representations of finite state machines for an informal description, including state diagrams and state machine charts.
  16. Have a understanding of the concept of machine equivalence, and be able to minimize a fully specified state table.
  17. Be able to take an informal word description of a sequential process and synthesize a state machine that performs the function.
  18. Know how to determine the clock period of a state machine.
  19. Understand the principles of register-transfer level (RTL) design and high-level state machines.
  20. Be able to take an informal word description of a digital circuit, design a high-level state machine for that circuit, and synthesize the high-level state machine to a final circuit implementation.
  21. Be able to design circuits using Verilog.