Lab 5 - Register-Transfer Level Design - Reaction Timer

In this lab, you will learn how to create RTL designs using Verilog by designing a reaction timer. You will first design the reaction timer as a high-level state machine using Verilog, the starting point for most RTL designs. You will then design the reactiont timer as connected datapath and controller.

The reaction timer circuit measures the time elapsed between the illumination a light and the pressing of a button by a user. The reaction timer has three inputs, a clock input clk, a reset input rst, and a button input B, and three outputs, a light enable output len, a 11-bit reaction time output rtime, and a slow output indicating the user was not fast enough. The reaction timer works as follows. On reset, the reaction timer waits for 10 seconds before illuminating the light by setting len to 1. The reaction timer then measures the length of time in milliseconds before the user presses the button B, outputting the time as a 11-bit binary number on rtime. If the user did not press the button within 2 seconds (2000 milliseconds), the reaction timer will set the output slow to 1 and output 2000 on rtime. Assume your clock input has a frequency of 1 kHz.

Lab Procedure

The following provides the steps that you must follow to complete this lab.

1. Design the reaction timer as a high-level state machine.
2. Test the reaction timer to ensure it functions correctly. Be sure to test both good reaction times and a reaction time that is too slow.
3. Design the same reaction timer as a connected datapath and controller. Your datapath should be structurally described, but the components used within your datapath can be designed behaviorally.
4. Test the connected datapath and controller design of reaction timer to ensure it functions correctly. Be sure to test both good reaction times and a reaction time that is too slow.

Demo

You must demo the following aspects or your designs to the TA.

1. Verilog code for the high-level state machine implementation of the reaction timer circuit.
2. Simulation waveforms demonstrating correct functionality of your high-level state machine design.
3. Verilog code for datapath and controller implementation of the reaction timer circuit.
4. Simulation waveforms demonstrating correct functionality of your datapath and controller design.

Lab Report

In addition to the standard lab report format, you must submit the following information.

1. Verilog code for the high-level state machine implementation of the reaction timer circuit.
2. Simulation waveforms demonstrating correct functionality of your high-level state machine design.
3. Verilog code for datapath and controller implementation of the reaction timer circuit.
4. Simulation waveforms demonstrating correct functionality of your datapath and controller design.
5. Describe the benefits of designing the reaction as a high-level state machine.