In this lab, you will design a 4-bit Even-Odd Up/Down Counter using several methods of implementation.
The Even-Odd Up/Down counter has a clock input, *clk*, a reset input, *rst*, count enable input,
*cen*, and an up/down control input, *dir*. The counter has a 4-bit output, *count*,
which outputs the current count as a 4-bit binary number. The Even-Odd counter operates as follows:

- When
*rst*= '1', the count should be reset to "0000". - Otherwise, if the
*cen*= '1', on every clock cycle the counter should count up when*dir*= '1' and count down when*dir*= '0'. - The Even-Odd counter cycles between couting solely even numbers and solely odd numbers. When couting up, starting from 0, the Even-Odd counter counts up only using even numbers, 0, 2, 4, ... . Upon reaching that last even number, 14, the counter begins counting up only using odd numbers, 1, 3, 5... .
- If
*cen*= '0' the counter should keep the present value.

The following provides the steps that you must follow to complete this lab.

- Behaviorally design the 4-bit Even-Odd Up/Down Counter as an Finite State Machine (FSM). You FSM design should consist of
two always procedures. The first always procedure, should implement the state register. The second
always procedure should implement the the FSM control logic. In the design of the FSM control logic, you must use
a
**case**statement to describe the combinational behavior associated with each state. Use the following module template for the FSM design:

module EvenOddCounter_FSM(clk, rst, cen, dir, count);

input clk, rst, cen, dir;

output [3:0] count; // this is how you declare a 4 bit signal initial Verilog

reg [3:0] count;

// parameter used to define states

// Define the remaining states for your FSM here

parameter S_0 = 4'b0000,

S_1 = 4'b0001,

// state registers for current state and next state

reg [3:0] currentstate;

reg [3:0] nextstate;

// state register procedure with asynchronous reset

always @(posedge rst or posedge clk)

begin

if (rst==1) // initial state

currentstate <= S_0;

else

currentstate <= nextstate;

end

// combinational logic procedure for FSM control logic

always @(currentstate or cen or dir)

begin

case (currentstate)

S_0: begin

// complete logic for state S_0

end

S_1: begin

// complete logic for remaining states

end

endmodule - Test your behavioral FSM design be simulating the functionality of the Even-Odd Up/Down Counter for several
possible control configuration. You must test the following aspects of your counter design:
- Fully test the upward counting of the counter through all possible values. Ensure that the counter properly transitions from even to odd values, and from odd to even values.
- Fully test the downward counting of the counter through all possible values. Ensure that the counter properly transitions from even to odd values, and from odd to even values.
- Test the your counter properly resets to "0000" whenever
*rst*= '1'. Be sure to test the reset functionality when the count is at a non-zero number. - Test that whenever
*cen*= '0' the counter retains its present value. Be sure to test the count enable when the count is at a non-zero number.

- Design the same 4-bit Even-Odd Up/Down Counter as a structural specified FSM design with
two structurally connected components implementing the state register and combinational
FSM control logic, respectively. The state register and control
logic components can be implemented behaviorally. In designing the control
logic component, you must behaviorally specify the functionality by determining
the Boolean equations for each output or the component. In other words, do
**NOT**use if-then-else or case statements in your design. Use the following module templates for your design:

// state register component with asynchronous reset

module stateregsiter(clk, rst, nextstate, currentstate);

input clk, rst;

input [3:0] nextstate;

output [3:0] currentstate;

reg [3:0] currentstate;

always @(posedge rst or posedge clk)

begin

// your code goes here

end

endmodule

// combinational logic component for FSM control logic

module fsmcontrol(cen, dir, currentstate, nextstate, count);

input cen, dir;

input [3:0] currentstate;

output [3:0] nextstate;

output [3:0] count;

reg [3:0] nextstate;

reg [3:0] count;

always @(currentstate or cen or dir)

begin

// your code goes here

end

endmodule

- Test your structural FSM design by simulating the functionality of the Even-Odd Up/Down Counter using the same test procedure as before.

You must demo the following aspects or your decoder designs to the TA.

- Verilog code for FSM design of the 4-bit Even-Odd Up/Down counter.
- Simulation waveforms demonstrating correct functionality for behavioral FSM design of the 4-bit Even-Odd Up/Down counter.
- Verilog code for structural FSM design of the 4-bit Even-Odd Up/Down counter.
- Simulation waveforms demonstrating correct functionality for structural FSM design of the 4-bit Even-Odd Up/Down counter.
- You must demonstrate the the behavioral and structural designs are equivalent.

In addition to the standard lab report format, you must submit the following information.

- Verilog code for behavioral and structural 4-bit Even-Odd Up/Down counter designs.
- Simulation waveforms demonstrating correct functionality for the behavioral and
structural Even-Odd Up/Down counter designs.
*Your waveforms should be identical.*