Lab 1 - Introduction to Verilog and Verilog Simulation

In this lab, you will design a library of basic logic gates including a 2-input AND gate, a 2-input OR gate, and an inverter (INV gate). Using these basic components, one can build any combinational logic circuit.

Lab Procedure

The following provides the steps that you must follow to complete this lab.

1. Follow the Verilog tutorial to design a 2-input AND gate. Test your design by exhaustively simulating all possible input combinations.
2. Design a 2-input OR gate. Test your design by exhaustively simulating all possible input combinations.
3. Design an inverter (INV gate). Test your design by exhaustively simulating all possible input combinations.

Demo

You must demo the following aspects or your NAND gate design to the TA.

1. Verilog code for AND, OR, and INV gates.
2. Simulation waveforms demonstrating correct functionality for the AND, OR, and INV gates for all possible inputs.

Lab Report

In addition to the standard lab report format, you must submit the following information.

1. Verilog code for AND gate design.
2. Verilog code for OR gate design.
3. Verilog code for INV gate design.
4. Simulation waveforms demonstrating correct functionality for the AND, OR, and INV gates for all possible inputs.