Roman Lysecky (firstname.lastname@example.org)
Office Hours: MW 1:00-2:00PM or by appointment.
Office: ECE 320F
MWF 12:00-12:50PM, ILC 140
|Section 1:||M 2:00PM-4:50PM,||ECE 301,||TA: Annapoorna Krishnaswamy|
|Section 2:||T 8:00AM-10:50AM,||ECE 301,||TA: Julian Sosa|
|Section 3:||T 2:00PM-4:50PM,||ECE 301,||TA: Julian Sosa|
|Section 4:||W 2:00PM-4:50PM,||ECE 301,||TA: Annapoorna Krishnaswamy|
|Section 5:||T 11:00AM-1:50PM,||ECE 301,||TA: Haiyong Zhang|
|Section 6:||R 11:00AM-1:50PM,||ECE 301,||TA: Haiyong Zhang|
|Section 7:||R 2:00PM-4:50PM,||ECE 301,||TA: Julian Sosa|
|Section 8:||F 2:00PM-4:50PM,||ECE 301,||TA: Annapoorna Krishnaswamy|
Haiyong Zhang, (email@example.com), Office Hours: M 3:30-4:30PM, Carrel 19, ECE320
Julian Sosa, (firstname.lastname@example.org)
Annapoorna Krishnaswamy, (email@example.com)
Fundamentals of Digital Logic with Verilog Design, Stephen Brown, Zvonko Vranesic, McGraw-Hill
McGraw-Hill's Book Website
Digital Design, Frank Vahid, John Wiley and Sons
Frank Vahid's Book Website
John Wiley and Sons' Book Website
Grading for the class will be performed on an individual basis. You will not
be competing with the other students for your grade. If all students do well
in the class, it is possible everyone will get an A. Your grade is only
dependent on the effort you put into the class. Letter grades will be
assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B,
70% and above to a C, 60% and above to a D, and less than 60% to an E.
The grading will be based on a weighted sum as follows:
Complete Course Syllabus
Punctuality: Please arrive on-time to class.
Academic Dishonestly: Any academic dishonesty will no be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Please consult the UA Code of Academic Integrity.
Reading: Be prepared. Read over the material being covered in lecture before coming to class. For the most part, the lectures will follow the organization of the book. Any planned deviations from this order will be announced beforehand.
Regrades: All requests for regrades must be submitted in writing within one week of the distribution of graded material. Problems requested to be regraded will be regraded in their entirety, which could possibly result in a lower score for the requested problem. Other problems within the same assignment might also be regraded, but such regrades will not negatively impact your score, i.e., regrades for problems not specifically requested will NOT result in a lower score.
Cell Phones: Please turn your cell phone off before you come to class.
Late Homeworks: Late homework assignments will be accepted for a maximum of two days after the due date. For each day your assignment is late, 10% of the total possible points will be deducted from your score.
SUBJECT TO CHANGE
|M||Aug 22:||Course Overview, Introduction to Digital Logic Design, (Chapter 1), PDF|
|W||Aug 24:||Introduction to Digital Logic Design (cont.), Basic Logic Gates, (Sections 2.1-2.4, 3.1-3.3), PDF|
|F||Aug 26:||Combinational Logic, Boolean Algebra, (Sections 2.5-2.7), PDF|
|M||Aug 29:||Combinational Logic Design Process, Common Components, (Sections 2.8, 6.1-6.2), PDF|
|W||Aug 31:||Combinational Logic Design Process, Common Components (cont.), (Sections 2.8, 6.1-6.2), PDF|
|F||Sep 02:||No Class|
|M||Sep 05:||No Class (Labor Day)|
|W||Sep 07:||Introduction to Sequential Logic, Basic Storage Element, (Sections 7.1-7.7), PDF|
|F||Sep 09:||Basic Register Design, Controllers, Sequential Logic Design Process, (Sections 7.8, 8.1-8.4), PDF|
|M||Sep 12:||Basic Register Design, Controllers, Sequential Logic Design Process (cont.), (Sections 7.8, 8.1-8.4), PDF|
|W||Sep 14:||Sequential Logic Design Process: Common Pitfalls and Additional Considerations, (Sections 7.8, 8.1-8.4), PDF|
|F||Sep 16:||Parallel Load, Shift, and Multifunction Registers, (Sections 7.8-7.10), PDF|
|M||Sep 19:||Parallel Load, Shift, and Multifunction Registers (cont.), (Sections 7.8-7.10), PDF|
|W||Sep 21:||Combinational Logic Design Review|
|F||Sep 23:||Adders: Half-Adder, Full-Adder, Carry-Ripple Adder,(Sections 5.1-5.2), PDF|
|M||Sep 26:||Adders: Half-Adder, Full-Adder, Carry-Ripple Adder (cont.), (Sections 5.1-5.2), PDF|
|F||Sep 30:||Sequential Logic Design Review|
|M||Oct 03:||Midterm 1|
|W||Oct 05:||No Class|
|F||Oct 07:||Shifters, Comparators, PDF|
|M||Oct 10:||Incrementers, Counters, Multipliers, (Sections 5.6, Section 7.9), PDF|
|W||Oct 12:||Incrementers, Counters, Multipliers (cont.), (Sections 5.6, Section 7.9), PDF|
|F||Oct 14:||Subtractors, Overflow, ALUs, Register Files, (Sections 5.3), PDF|
|M||Oct 17:||Subtractors, Overflow, ALUs, Register Files (cont.), (Sections 5.3), PDF|
|W||Oct 19:||Introduction to Register-Transfer-Level (RTL) Design, PDF|
|F||Oct 21:||RTL Design Method, PDF|
|M||Oct 24:||RTL Design Method, RTL Design Examples, PDF|
|W||Oct 26:||RTL Design Examples, Pitfalls and Good Practices, Control and Data Dominated RTL Design, PDF|
|F||Oct 28:||RTL Design Examples, Pitfalls and Good Practices, Control and Data Dominated RTL Design (cont.), PDF|
|M||Oct 31:||RTL Design: Determining Clock Frequency, Behavioral RTL Design: C to Gates, PDF|
|W||Nov 02:||Memories: RAM/ROM/PROM, PDF|
|M||Nov 07:||No Class|
|W||Nov 09:||Midterm 2|
|F||Nov 11:||No Class (Veterans Day)|
|M||Nov 14:||Optimization: Two-Level Minimization, Karnaugh Maps, PDF|
|W||Nov 16:||Optimization: Exact and Heuristic Two-Level Minimization, Multi-Level Optimization, PDF|
|F||Nov 18:||Optimization: Exact and Heuristic Two-Level Minimization, Multi-Level Optimization (cont.), PDF|
|M||Nov 21:||Optimization: Mealy vs. Moore FSMs, Carry-Lookahead Adders, PDF|
|W||Nov 23:||No Class|
|F||Nov 25:||No Class (Thanksgiving Break)|
|M||Nov 28:||Optimization: Carry-Lookahead Adders (cont.), PDF|
|W||Nov 30:||Implementation: Full-Custom ICs, Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), PDF|
|F||Dec 02:||Implementation: Field-Programmable Gate Arrays (FPGAs), Programmable Logic Devices (PLDs), PDF|
|M||Dec 05:||No Class, Extended Office Hours - 12:00PM-2:00PM, Note: Homework 5 due by 12:15PM in my mailbox or office.|
|W||Dec 07:||Review for Final|
|F||Dec 16:||Final 11:00AM-1:00PM|
Homework 1, Due September 12 (beginning of class)
Homework 2, Due September 26 (beginning of class)
Homework 3, Due October 21(beginning of class)
Homework 4, Due November 4(beginning of class)
Homework 5, Due December 5(beginning of class)
Quiz 1 Week of September 19-23, Solutions
Quiz 2 Week of October 24-28
Midterm 1 Sample Problems, Note: Midterm problems are not limited to theses sample problems.
Final Sample Problems, Note: Final problems are not limited to theses sample problems.
Labs must be finished on-time. Late labs will not be accepted. A lab report, using the specified lab report format, is required for all lab assignments, including tutorials, and is due at the beginning of the following lab period after the lab is due. Individual labs may also require additional information such as schematics, simulations, manually performed tasks, or a summary of results. Please be sure to include this information in your lab report. Your lab report will count for 20% of each lab score.
Students should work in groups of two for laboratory assignments. However, students have the option of working on their own if computing resources permit. You must choose your lab partner during the first lab and inform your TA of your selection. You lab partner will remain the same for the during of the semester. Please choose your lab partner wisely.
|Lab 1 (Starts Aug 29 - Sep 2)||Introduction to Verilog and Verilog Simulation||50|
|Lab 2 (Starts Sep 12 - Sep 16)||Structural and Behavioral Design of a 3x8 Decoder||100|
|Lab 3 (Starts Sep 26 - Sep 30)||4-bit Even-Odd Up/Down Counter||100|
|Lab 4 (Starts Oct 10 - Oct 14)||Datapath Component Design - Adder and Comparator Design||100|
|Lab 5 (Starts Oct 24 - Oct 28)||Register-Transfer Level Design - Reaction Timer||150|