Roman Lysecky (rlysecky@cs.ucr.edu)
Office Hours: TR 2:00-3:00 PM or by appointment.
Office: Surge 348
MW 1:10-2:00 PM, Sproul 2339
F 2:10-3:00 PM, Bourns A171
MW 2:10-5:00 PM, Surge 173
Som Neema, (sneema@cs.ucr.edu)
Office Hours: TBA.
Surge 282
Modern VLSI Design: System-on-Chip Design by Wayne Wolf, Third Edition, Prentice Hall PTR
Wayne Wolf's Book Website
Prentice Hall PTR Book Website
Grading for the class will be performed on an individual basis. You will not
be competing with the other students for your grade. If all students do well
in the class, it is possible everyone will get an A. Your grade is only
dependent on the effort you put into the class. Letter grades will be
assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B,
70% and above to a C, 60% and above to a D, and less than 60% to an F.
The grading will be based on a weighted sum as follows:
| 30% | Final | |
| 20% | Midterm | |
| 10% | Quizzes | |
| 10% | Homeworks | |
| 30% | Lab Assignments |
Punctuality: Please arrive on-time to class.
Academic Dishonestly: Any academic dishonesty will no be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own.
Reading: Be prepared. Read over the material being covered in lecture before coming to class. For the most part, the lectures will follow the organization of the book. Any planned deviations from this order will be announced beforehand.
Lab Attendance: Lab attendance is mandatory for the entire lab period during which you should be working on course related material. If you finish a lab assignment early, work can always work ahead on the next assignment.
Class Mailing List: The class mailing list and newsgroup will be used for all course related correspondence such as course announcements. Furthermore, please address all course related questions regarding lectures, homework, labs, etc. to the course mailing list or newsgroup.
Cell Phones: Please turn your cell phone off before you come to class.
SUBJECT TO CHANGE
| M | Jan 05: | Course Overview, Introduction to VLSI Design, (Chapter 1), PDF | |
| W | Jan 07: | Fabrication, Transistor Structures, Basic Transistor Behavior, (Chapter 2), PDF | |
| F | Jan 09: | Transistor Characteristics, (Chapter 2), PDF | |
| M | Jan 12: | Wires, Vias, and Parasitics, (Chapter 2), PDF | |
| W | Jan 14: | Designs Rules and Stick Diagrams, (Chapter 2), PDF | |
| F | Jan 16: | Combinational Logic Functions and CMOS Logic Gates, (Chapter 3) PDF | |
| M | Jan 19: | No Class | |
| W | Jan 21: | Electrical Properties of Combinational Gates, (Chapter 3) PDF | |
| F | Jan 23: | Electrical Properties of Combinational Gates (continued), (Chapter 3) PDF | |
| M | Jan 26: | Wire Delay, Buffer Insertion, Etc., (Chapter 3) PDF | |
| W | Jan 28: | Psuedo nMOS Gates, DCVS Logic, Domino Gates, (Chapter 3) PDF | |
| F | Jan 30: | Layout, Channel Routing, Simulation, (Chapter 4) PDF | |
| M | Feb 02: | Combinational Network Delay, Logic Optimization, (Chapter 4) PDF | |
| W | Feb 04: | Transistor Sizing, (Chapter 4) PDF | |
| F | Feb 06: | Interconnect Design, Crosstalk, Power Optimization, (Chapter 4) PDF | |
| M | Feb 09: | Switch Networks, Combinational Testing, (Chapter 4) PDF | |
| W | Feb 11: | Memory Elements, Basics of Sequential Machines, (Chapter 5) PDF | |
| F | Feb 13: | Clocking Disciplines, (Chapter 5) PDF | |
| M | Feb 16: | No Class | |
| W | Feb 18: | Midterm | |
| F | Feb 20: | Sequential Machine Design, (Chapter 5) PDF | |
| M | Feb 23: | State Assignment, Power Optimization, Design Validation, Sequential Testing, (Chapter 5) PDF | |
| W | Feb 25: | FPGA Fabric Architecture PDF | |
| F | Feb 27: | SRAM-based FPGA Fabrics PDF | |
| M | Mar 01: | Shifters, Adders, ALU, (Chapter 6) PDF | |
| W | Mar 03: | Multipliers, (Chapter 6) PDF | |
| F | Mar 05: | Memories, Datapaths, PLAs, (Chapter 6) PDF | |
| M | Mar 08: | TBA | |
| W | Mar 10: | Review for Final | |
| F | Mar 12: | Final |
Homework 1: 1-4, 2-2, 2-4, 2-9, 2-13
Homework 2: 3-1, 3-5, 3-6, 3-19, 3-21
Homework 3: 4-2, 4-4, 4-5, 4-7, 4-8
Homework 4: 5-4, 5-15
Labs must be finished on-time. Late labs will not be accepted. A lab report, using the specified lab report format is required for all lab assignments, including tutorials, and is due at the beginning of the following lab period after the lab is due. Individual labs may also require additional information such as schematics, layout, or a summary of results. Please be sure to include this information in your lab report. Your lab report will count for 20% of each lab score.
| Date | Description | Points | |
|---|---|---|---|
| Week 1 | Jan 05 (M) | Lab/Tutorial 1 - Introduction to Cadence Schematic Design/Simulation Demo and Lab Report due at the end of lab, Jan 14. |
50 |
| Jan 07 (W) | Lab/Tutorial 2 - Introduction to Cadence Layout Design Demo and Lab Report due at the end of lab, Jan 14. |
50 | |
| Week 2 | Jan 12 (M) | Lab 3 - NAND Gate Transistor/Layout Design | 100 |
| Jan 14 (W) | Lab 3 (Continued) - NAND Gate Transistor/Layout Design Due at the end of lab. |
||
| Week 3 | Jan 19 (M) | No Lab | |
| Jan 21 (W) | Lab 4 - 4-bit Adder Design | 200 | |
| Week 4 | Jan 26 (M) | Lab 4 (Continued) - 4-bit Adder Design | |
| Jan 28 (W) | Lab 4 (Continued) - 4-bit Adder Design Due at the end of lab. |
||
| Week 5 | Feb 02 (M) | Lab 5 - 1-bit SRAM Memory Cell Design | 100 |
| Feb 04 (W) | Lab 5 (Continued) - 1-bit SRAM Memory Cell Design Due at the end of lab. |
||
| Week 6 | Feb 09 (M) | Lab 6 - 4-bit SRAM Shift Register | 200 |
| Feb 11 (W) | Lab 6 (Continued) - 4-bit SRAM Shift Register | ||
| Week 7 | Feb 16 (M) | No Lab | |
| Feb 18 (W) | Lab 6 (Continued) - 4-bit SRAM Shift Register Due at the end of lab. |
||
| Week 8 | Feb 23 (M) | Lab 7 - Field Programmable Gate Array (FPGA) Configurable Logic Block (CLB) Design | 300 |
| Feb 25 (W) | Lab 7 (Continued) - FPGA CLB Design | ||
| Week 9 | Mar 01 (M) | Lab 7 (Continued) - FPGA CLB Design | |
| Mar 03 (W) | Lab 7 (Continued) - FPGA CLB Design | ||
| Week 10 | Mar 08 (M) | Lab 7 (Continued) - FPGA CLB Design | |
| Mar 10 (W) | Lab 7 (Continued) - FPGA CLB Design Due at the end of lab. |