Publications

Patents

  1. F. Vahid, R. Lysecky, G. Stitt. Warp Processor for Dynamic Hardware/Software Partitioning. US Patent 7,356,672, 2008.


Books

  1. R. Lysecky, A. Lizarraga. Programming in Java. Zyante, 2013.
  2. R. Lysecky, F. Vahid. Programming in C. Zyante, 2012.
  3. F. Vahid, R. Lysecky. Programming in C++. Zyante, 2012.
  4. F. Vahid, R. Lysecky. VHDL for Digital Design. John Wiley and Sons, 2007.
  5. F. Vahid, R. Lysecky. Verilog for Digital Design. John Wiley and Sons, 2007.


Book Chapters

  1. R. Lysecky, K. Shankar. Methods for Non-Intrusive Dynamic Application Profiling and Soft Error Detection. In Embedded and Networking Systems Design, Software, and Implementation, Edited by Gul Khan and Krzysztof Iniewski, Chapman and Hall/CRC, 2013.
  2. A. Gordon-Ross, S. Lysecky, R. Lysecky, A. Munir, A. Shenoy, J. Hiner. Dynamic Profiling and Optimiaation Methodologies for Sensor Networks. In Building Sensor Networks From Design to Applications, Edited by Ioanis Nikolaidis and Krzysztof Iniewski, CRC Press, 2013.
  3. R. Lysecky. Hardware Description Languages in Digital Design by F. Vahid, John Wiley and Sons, 2006.


Journal Publications

  1. J. C. Lee, J. Vance, and R. Lysecky. Hardware-based Event Stream Ordering for System-level Observation Framework. IEEE Embedded Systems Letters (ESL), Accepted for Publication, 2014.
  2. J. Sametinger, J. Rozenblit, R. Lysecky, P. Ott. Security Challenges for Medical Devices. Communication of ACM (CACM), Accepted for Publication, 2014.
  3. J. Sun, R. Lysecky, K. Shankar, A. Kodi, A. Louri, J. Roveda. Workload Assignment Considering NBTI Degradation in Multi-core Systems, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 10, No. 1, Article 4, pp. 1-22, 2014.
  4. A. Lizarraga, R. Lysecky, S. Lysecky, A. Gordon-Ross. Dynamic Profiling and Fuzzy Logic Based Optimization of Sensor Networks Platforms. ACM Transactions on Embedded Computing Systems (TECS), Vol. 13, No. 3, Article 51, pp. 1-29, 2013.
  5. J. Mu, K. Shankar, R. Lysecky. Profiling and Online System-Level Performance and Power Estimation for Dynamically Adaptable Embedded Systems. ACM Transactions on Embedded Computing Systems (TECS), Vol. 12, No. 3, Article 85, pp. 1-20, 2013.
  6. A. Munir, A. Gordon-Ross, S. Lysecky, R. Lysecky. A Lightweight Dynamic Optimization Methodology and Application Metrics Estimation Model for Wireless Sensor Networks. Sustainable Computing, Informatics and Systems (SUSCOM), Vol. 3, No. 2, pp. 94108, 2013.
  7. A. Lizarraga, L. Ding, J. Hiner, R. Lysecky, S. Lysecky, A. Gordon-Ross. ATLeS-SN A Modular Simulator for Wireless Sensor Networks. Design Automation for Embedded Systems (DAEM), Vol. 16, No. 4 , pp. 265-291, 2012.
  8. J. Sun, R. Zheng, J. Velamala, Y. Cao, R. Lysecky, K. Shankar, J. Roveda. A Self-tuning Design Methodology for Power-efficient Multi-core Systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 1, Article 4, pp. 1-24, 2012.
  9. A. Munir, A. Gordon-Ross, S. Lysecky, R. Lysecky. A One-Shot Dynamic Optimization Methodology and Application Metrics Estimation Model for Wireless Sensor Networks. IARIA Journal of Advances in Networks and Services, IARIA International Journal on Advances in Networks and Services (IJANS), Vol. 4, No. 3 & 4, pp. 278-291, 2012.
  10. A. Nair, K. Shankar, R. Lysecky. Efficient Hardware-Based Non-Intrusive Dynamic Application Profiling. ACM Transactions on Embedded Computing Systems (TECS), Vol. 10, No. 3, Article 32, pp. 1-22, 2011. PDF
  11. K. Shankar, R. Lysecky. Control Focused Soft Error Detection for Embedded Applications, IEEE Embedded Systems Letters (ESL), Vol. 2, No. 4, pp 127-130, 2010. PDF
  12. A. Shenoy, J. Hiner, S. Lysecky, R. Lysecky, A. Gordon-Ross. Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks. IEEE Embedded Systems Letters, Vol. 2, No. 1, pp. 10-13, 2010. PDF
  13. R. Kalra, R. Lysecky. Configuration Locking and Schedulability Evaluation for Reduced Reconfiguration Overheads of Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 18, No. 4, pp. 671-674, 2010. PDF
  14. J. Mu, R. Lysecky. Autonomous Hardware/Software Partitioning and Voltage/Frequency Scaling for Low-Power Embedded Systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 15, No. 1, Article 2, pp. 1-20, 2009. PDF
  15. L. Saldanha, R. Lysecky. Float-to-Fixed and Fixed-to-Float Hardware Converters for Rapid Hardware/Software Partitioning of Floating Point Software Applications to Static and Dynamic Fixed Point Coprocessors. Journal on Design Automation of Embedded Systems, Vol. 13, No. 3, pp. 139-157, 2009. PDF
  16. R. Lysecky, F. Vahid. Design and Implementation of a MicroBlaze-based Warp Processor. ACM Transactions on Embedded Computing Systems (TECS), Vol. 8, No. 3, Article 22, pp. 1-22, 2009. PDF
  17. R. Lysecky. Scalability and Parallel Execution of Warp Processing - Dynamic Hardware/Software Partitioning. International Journal on Parallel Programming, Vol. 36, No.5, pp. 478-492, October 2008. PDF
  18. F. Vahid, G. Stitt, R. Lysecky. Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. IEEE Computer, Vol. 41, No. 7, pp. 40-46, July 2008. PDF
  19. R. Lysecky, G. Stitt, F. Vahid. Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 3, pp. 659 - 681, 2006. PDF
  20. C. Zhang, F. Vahid, R. Lysecky. A Self-Tuning Cache Architecture for Embedded Systems. ACM Transactions on Embedded Computing Systems (TECS), Vol. 3, No. 2, pp. 407-425, May 2004. PDF
  21. R. Lysecky, S. Cotterell, F. Vahid. A Fast On-Chip Profiler Memory using a Pipelined Binary Tree. IEEE Transaction on Very Large Scale Integration (TVLSI), Vol. 12, No. 1, pp. 120-122, January 2004. PDF
  22. F. Vahid, R. Lysecky, C. Zhang, G. Stitt. Highly Configurable Platforms for Embedded Computing Systems. Microelectronics Journal, Vol. 34, No. 11, pp. 1025-1029, 2003. PDF
  23. R. Lysecky, F. Vahid. Pre-fetching for Improved Bus Wrapper Performance in Cores. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 7, Number 1, pp. 58-90, January 2002. PDF


Conference and Workshop Publications (refereed)

  1. S. Lu, M. Seo, and R. Lysecky. Timing-based Anomaly Detection in Embedded Systems. Asia South Pacific Design Automation Conference (ASP-DAC), Accepted for Publication, 2014.
  2. J. C. Lee, R. Lysecky. Area-Efficient Event Stream Ordering for Runtime Observability of Embedded Systems. IEEE/ACM Design Automation Conference (DAC), Article 130, pp. 1-6, 2014.
  3. T. Pifer, D. Schwartz, R. Lysecky, C. Seo, B. Zeigler. Discrete Event System Specification, Synthesis, and Optimization of Low-Power FPGA-based Embedded Systems. International Conference on Field-Programmable Technology (ICFPT), pp. 98-105, 2013.
  4. N. Sandoval, C. Mackin, S. Whitsitt, R. Lysecky, J. Sprinkle. Runtime Hardware/Software Task Transition Scheduling for Runtime-Adaptable Embedded Systems. International Conference on Field-Programmable Technology (ICFPT), pp. 342-345, 2013.
  5. R. Lysecky, N. Sandoval, S. Whitsitt, C. Mackin, J. Sprinkle. Efficient Reconfiguration Methods to Enable Rapid Deployment of Runtime Reconfigurable Systems. Asilomar Conference on Signals, Systems and Computers, 2013.
  6. N. Sandoval, C. Mackin, S. Whitsitt, R. Lysecky, J. Sprinkle. System Throughput Optimization and Runtime Communication Middleware Supporting Dynamic Software-Hardware Task Migration in Data Adaptable Embedded Systems. IEEE International Conference on Engineering of Computer-Based Systems (ECBS), 2013.
  7. L. Ding, A. Lizarraga, S. Lysecky, R. Lysecky, A. Gordon-Ross. Accuracy-Guided Runtime Adaptive Profiling Optimization of Wireless Sensor Networks. IEEE International Conference on Engineering of Computer-Based Systems (ECBS), 2013.
  8. J. C. Lee, R. Lysecky. System Observation of Blocking, Non-Blocking, and Cascading Events for Runtime Monitoring of Real-Time Systems. IEEE International Conference on Engineering of Computer-Based Systems (ECBS), 2013.
  9. S. Whitsitt, J. Sprinkle, R. Lysecky. An Overseer Control Methodology for Data Adaptable Embedded Systems. International Workshop on Multi-Paradigm Modeling (MPM), pp. 1-6, 2012.
  10. J.C. Lee, F. Kouteib, R. Lysecky. Event-Driven Framework for Configurable Runtime System Observability for SOC Designs. International Test Conference (ITC), pp. 1-10, 2012.
  11. J. Mu, R. Lysecky. Adaptive Online Heuristic Performance Estimation and Power Optimization for Reconfigurable Embedded Systems. International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), pp. 265-274, 2012.
  12. V. K. Nileshwar, R. Lysecky. SNR Analysis Approach for Hardware/Software Partitioning using Dynamically Adaptable Fixed Point Representation, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 27-32, 2012.
  13. A. Milakovich, V. S. Gopinath, R. Lysecky, J. Sprinkle. Automated Software Generation and Hardware Coprocessor Synthesis for Data-Adaptable Reconfigurable Systems IEEE International Conference on Engineering of Computer-Based Systems (ECBS), pp. 15-23, 2012.
  14. A. Munir, A. Gordon-Ross, S. Lysecky, R. Lysecky. Online Algorithms for Wireless Sensor Netowrks Dynamic Optimization. IEEE Consumer Communications and Networking Conference (CCNC), pp. 180-187, 2012.
  15. V. S. Gopinath, J. Sprinkle, R. Lysecky. Modeling of Data Adaptable Reconfigurable Embedded Systems. IEEE Workshop on Model-Based Development for Computer Based Systems, pp. 276-283, 2011. PDF
  16. J. C. Lee, A. S. Gardner, R. Lysecky. Hardware Observability Framework for Minimally Intrusive Online Monitoring of Embedded Systems. IEEE International Conference on Engineering of Computer-Based Systems (ECBS), pp. 52-60, 2011. PDF
  17. S. Mahadevan, V. S. Gopinath, R. Lysecky, J. Sprinkle, J. Rozenblit, M. W. Marcellin. Hardware/Software Communication Middleware for Data Adaptable Embedded Systems. IEEE International Conference on Engineering of Computer-Based Systems (ECBS), pp. 34-43, 2011. PDF
  18. A. Milakovich, V. Gopinath, R. Lysecky, J. Sprinkle. Automated Software Generation and Hardware Coprocessor Synthesis for Data-Adaptable Reconfigurable Systems. Workshop on Adaptive and Reconfigurable Embedded Systems (APRES), 2011.PDF
  19. Mu, J., R. Lysecky. Profile Assisted Online System-Level Performance and Power Estimation for Dynamic Reconfigurable Embedded Systems. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 737-742, 2011.
  20. J. Sun, R. Zheng, J. Velamala, Y. Cao, R. Lysecky, K. Shankar, J. Roveda. A Self-Evolving Design Methodology for Power Efficient Multi-core Systems. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 264-268, 2010. PDF
  21. A. Munir, A. Gordon-Ross, S. Lysecky, R. Lysecky. . A One-Shot Dynamic Optimization Methodology for Wireless Sensor Networks. International Conference on Mobile Ubiquitous Computing, Systems, Services (UBICOMM), 2010.
    Received Best Paper Award
  22. A. Munir, A. Gordon-Ross, S. Lysecky, R. Lysecky. A Lightweight Dynamic Optimization Methodology for Wireless Sensor Networks. IEEE International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob), pp. 129-136, 2010.
  23. J. Hiner, A. Shenoy, R. Lysecky, S. Lysecky, A. Gordon-Ross. Transaction-Level Modeling for Sensor Networks Using SystemC. IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), pp. 197-204, 2010. PDF
  24. J. Sun, R. Lysecky, K. Shankar, A. Kodi, A. Louri, J. Wang. Workload Capacity Considering NBTI Degradation in Multi-core Systems. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 450-455, 2010. PDF
  25. K. Shankar, R. Lysecky. Non-Intrusive Dynamic Application Profiling for Multitasked Applications. Design Automation Conference (DAC), pp. 130-135, 2009.PDF
  26. L. Saldanha, R. Lysecky. Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Point Coprocessor Circuits. International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), pp. 49-54, 2008.PDF
    Received Best Paper Award
  27. A. Nair, R. Lysecky. Non-Intrusive Dynamic Application Profiler for Detailed Loop Execution Characterization. International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), pp. 23-30, 2008.PDF
  28. M. Hammerquist, R. Lysecky. Design Space Exploration for Application-Specific FPGAs in System-on-a-Chip Designs. IEEE International SOC Conference (SOCC), pp. 279-282, 2008. PDF
  29. R. Lysecky. Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 141-146, 2007. PDF
  30. D. Sheldon, R. Kumar, R. Lysecky, F. Vahid, D. M. Tullsen. Application-Specific Customization of Parameterized FPGA Soft-Core Processors. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 261-268, 2006. PDF
  31. D. Sheldon, R. Kumar, F. Vahid, D. M. Tullsen, R. Lysecky. Conjoining Soft-Core FPGA Processors. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 694-701, 2006. PDF
  32. R. Lysecky, F. Vahid, S. Tan. A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 57-62, 2005. PDF
  33. R. Lysecky, F. Vahid. A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 18-23, 2005. PDF
  34. Lysecky, R., K. Miller, F. Vahid, K. Vissers, K. POSTER: Firm-core Virtual FPGA for Just-in-Time FPGA Compilation. ACM International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 271-271, 2005. Extended Paper PDF
  35. R. Lysecky, F. Vahid, S. Tan. Dynamic FPGA Routing for Just-in-Time Compilation. IEEE/ACM Design Automation Conference (DAC), pp. 954-959, 2004. PDF
  36. R. Lysecky, F. Vahid. A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 480-485, 2004. PDF
  37. C. Zhang, F. Vahid, R. Lysecky. A Self-Tuning Cache Architecture for Embedded Systems. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 16-20, 2004. PDF
  38. R. Lysecky, F. Vahid. A Codesigned On-Chip Logic Minimizer. IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 109-113, 2003. PDF
  39. R. Lysecky, F. Vahid. On-Chip Logic Minimization. IEEE/ACM 40th Design Automation Conference (DAC), pp. 334-337 2003. PDF
  40. G. Stitt, R. Lysecky, F. Vahid. Dynamic Hardware/Software Partitioning: A First Approach. IEEE/ACM 40th Design Automation Conference (DAC), pp. 250-255, 2003. PDF
  41. R. Lysecky, S. Cotterell, F. Vahid. A Fast On-Chip Profiler Memory. IEEE/ACM 39th Design Automation Conference (DAC), pp. 28-33, pp. 28-33, 2002. PDF
  42. G. Stitt, F. Vahid, T. Givargis, R. Lysecky. A First-step Towards an Architecture Tuning Methodology for Low Power. IEEE/ACM International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), pp. 187-192, Novemeber 2000. PDF
  43. R. Lysecky, F. Vahid, T. Givargis. Experiments with the Peripheral Virtual Component Interface. IEEE/ACM International Symposium on System Synthesis (ISSS), pp. 221-224, September 2000. PDF
  44. R. Lysecky, F. Vahid, T. Givargis. Techniques for Reducing Read Latency of Core Bus Wrappers. IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 84-91, March 2000. PDF
    Received Best Paper Award
  45. R. Lysecky, F. Vahid, T. Givargis, R. Patel. Pre-fetching for Improved Core Interfacing. IEEE/ACM International Symposium on System Synthesis (ISSS), pp. 51-55, 1999. PDF


Technical Reports

  1. Hammerquist, M. R. Lysecky. Technical Report on Design Space Exploration and CLB Customization for Application-Specific FPGAs. University of Arizona Technical Report UA-041010-RL-02, pp. 1-9, 2010. PDF
  2. Shankar, K., R. Lysecky. Technical Report on Non-Intrusive Dynamic Application Soft Error Detection. University of Arizona Technical Report UA-031510-RL-01, pp. 1-7, 2010. PDF
  3. J. Villarreal, R. Lysecky, S. Cotterell, F. Vahid. Loop Analysis of Embedded Applications. UC Riverside Technical Report UCR-CSE-01-03, 2001. PDF


Presentations

  1. R. Lysecky. Modeling and Codesign Methods for Data Adaptable Reconfigurable Embedded Systems, University of Arkansas, October 2011. (Invited Talk) PPT
  2. R. Lysecky. Hardware Observability Framework for Non-Intrusive Monitoring of Complex Embedded Systems, Workshop on Compiler Assisted System-on-Chip Assembly (CASA), October 2010. (Invited Talk) PPT
  3. R. Lysecky. Dynamic and Autonomous Software-to-Hardware Translation for High-Performance and Low-Power Embedded Computing, Computer Engineering and Computer Science Seminar, University of Arizona, Tucson, AZ, March 2009. (Invited Talk) PPT
  4. R. Lysecky. Autonomously Adaptive Computing: Coping with Scalability, Reliability, and Dynamicity in Future Generations of Computing, Kavli/NNIN Symposium on Computing, Cornell University, Ithaca, NY, October 2008 (Invited Talk) PPT