Short Bio

Roman Lysecky is an Associate Professor of Electrical and Computer Engineering at the University of Arizona. He received his B.S., M.S., and Ph.D. in Computer Science from the University of California, Riverside in 1999, 2000, and 2005, respectively. His research interests focus on embedded systems, with emphasis on runtime optimization, non-intrusive system observation methods for in-situ analysis of complex hardware and software behavior, data-adaptable system, and embedded system security. He was awarded the Outstanding Ph.D. Dissertation Award from the European Design and Automation Association (EDAA) in 2006 for New Directions in Embedded Systems. He received a CAREER award from the National Science Foundation in 2009 and five Best Paper Awards at the ASEE Annual Conference, ACM/IEEE International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), the ACM/IEEE Design Automation and Test in Europe Conference (DATE), the IEEE International Conference on Engineering of Computer-Based Systems (ECBS), and the International Conference on Mobile Ubiquitous Computing, Systems, Services (UBICOMM). He is an inventor on one US patent. He has coauthored five textbooks on VHDL, Verilog, C, C++, and Java programming. His recent textbooks, published with Zyante, utilize a web-native, interactive, and animated approach that has shown notable increases in student learning and course grades. He has also received multiple awards for Excellence at the Student Interface from the College of Engineering at the University of Arizona.

Recent News

  • August 23, 2016: NSF has funded a new project on TWC: Small: Time-Centric Modeling of Correct Behaviors for Efficient Non-intrusive Runtime Detection of Unauthorized System Actions with Co-PI Jerzy Rozenblit. National Science Foundation (NSF), CNS-1615890, $453,413, October 2016 September 2019.
Abstract: This project investigates formal timing-centric system behavior models that robustly capture the correct system execution behavior, which thereby enables efficient runtime detection of unauthorized system actions. The formal models will combine well-founded techniques relying on execution call graphs, sequence models, system timing requirements, and statistical analysis of execution times. Secure, non-intrusive, and efficient hardware-based identification will be developed to detect deviations from the timing and sequence characteristics defined within the nominal system behavior models. The project will investigate performance models to evaluate the area and energy overhead of our monitoring hardware. To maintain efficiency, systematic methods will de developed to evaluate and optimize the tradeoffs between security achieved by these methods and the area and energy overheads. This research will further investigate novel methods for analyzing the timing of networked embedded systems to separate the intrinsic software execution time from the incidental execution time resulting from the underlying hardware architecture, operating system, and physical environment.
  • August 01, 2016: NSF has funded a new project on CSR:Medium: Modeling and Synthesis for Application-Specific Systems-on-a-Chip. with PI Frank Vahid (UC Riverside) and Co-PI Tony Givargis (UC Irvine). National Science Foundation (NSF), CNS-1563652, $1,000,000, August 2016 July 2020.
Abstract: State-of-the-art computer chips cost tens of millions of dollars to build. Companies that build such chips make them as configurable as possible, so the same chip that is used in a digital TV application can also be used in a medical device application. However, engineers who use these chips have a hard time setting all the configurable features to get the chip's performance and power optimal for their one application. This project will investigate and develop techniques to automatically tune a state-of-the-art chip's many configurable features to serve any one particular application well, thus substantially improving performance and power for any application implemented on such a chip. The project will develop a unified computation model that ideally supports such techniques, empowering engineers to make best use of state-of-the-art chips. The project not only will improve the performance and power of a wide variety of popular devices, but also includes a web-based tool for capturing the unified computation model. Such a tool will positively impact university education as well as practicing engineers, and can catalyze research.
  • April 01, 2016: Army Research Office ARO has funded a new project on Theoretical Foundations, Modeling, and Exploration for Analyzing Power Obfuscation in Secure Embedded Systems with Co-PI Dr. Janet Wang. Army Research Office (ARO), W911NF-16-1-0130, $445,000, April 2016 March 2019.
Abstract: As embedded systems are at the heart of these mission-critical systems, verifying and maintaining the security and integrity of these devices is paramount. Side-channel attacks (SCAs) are a critical threat to the security of these systems. SCAs analyze variations in timing, power consumption, and electromagnetic radiation that can be exploited by attackers to extract critical information, e.g., cryptographic keys, from software operations. Although cryptography provides some level of security, SCAs demonstrate a critical weakness that must be properly addressed to secure embedded systems within mission critical systems. In this project, we aim at securing embedded systems by developing new mathematical models for precisely evaluating the susceptibility of embedded systems software and hardware to SCAs and the increased resilience to SCAs afforded by power obfuscation methods.
  • Here's a great video showing the benefits of the "Less text, more action" approach for zyBooks.

Recent Publications

  1. S. Sargur, R. Lysecky. Non-Intrusive Dynamic Profiler for Multicore Embedded Systems. Asia and South Pacific Design Automation Conference (ASP-DAC), Accepted, 2017.
  2. M. Seo and R. Lysecky. In-Situ Requirements Monitoring of Embedded Systems. IEEE Embedded Systems Letters (ESL), Vol. 8, No. 3, pp. 49-52, 2016.
  3. A. Lizarraga, R. Lysecky, J. Sprinkle. Model-based Fuzzy Logic Classifier Synthesis for Optimization of Data-Adaptable Embedded Systems. International Conference on InfoSymbiotics/DDDAS. 2016.
  4. A. Lizarraga, J. Sprinkle, R. Lysecky. Model-driven Optimization of Data-Adaptable Embedded Systems. IEEE Computer Software and Applications Conference (COMPSAC), 2016.
  5. Hyunsuk Nam, R. Lysecky. Latency, Power, and Security Optimization in Distributed Reconfigurable Embedded Systems. Reconfigurable Architecture Workshop (RAW), 2016.
  6. J. C. Lee and R. Lysecky. System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 20, No. 3, pp. 1-27, 2015.
  7. A. Edgcomb, F. Vahid, R. Lysecky. Students Learn More with Less Text that Covers the Same Core Topics. IEEE Frontiers in Education, 2015.
  8. S. Lu, R. Lysecky. Analysis of Control Flow Events for Timing-based Runtime Anomaly Detection. Workshop on Embedded Systems Security (WESS), 2015.