Recent Publications

Sumitted Paper and Technical Report

 

[1] R. Raghave, A. Kodi, A. Louri, and J. M. Wang, "A Robust High Speed Link Design for NoC at 65nm Technology Node," Technical Report, University of Arizona, 2008.[pdf]

 

[2] R.  Jiang, W. Fu, J. M. Wang, V. Lin and C. C-P. Chen, “A new, efficient statistical capacitance  variability modeling with orthogonal principle factor analysis,” IEEE Trans. on Microwave Theory Tech. Under review.

 

[3] K. Kumar, J. Kumar, and J. M. Wang, “Cluster based dynamic area-array i/o planning for flip chip technology,” Microelectronics Engineering. Under review.

 

[4] J. Liu, L. Zhang, T. Lin, J. Hong, J.M. Wang and C. C-P Chen, “Correlation-driven testing path reduction,”  ACM Trans. on Design and Automation of Electronic Systems. Under review

 

 

Books/chapters

 

[1]* J.M.Wang and E.S. Kuh, “Chebyshev expansion based interconnect modeling”,  Signal Propagation on Interconnect,  Kluwer  Book publisher, 2000

 

Journal Papers :

 

[1] Jin Sun, and J. M. Wang, “Predicting Analog Circuit Performance Based on  Importance of Uncertainties Date of Evaluation,” Transaction of the Institute of Electronics, Information and Communication Engineers (IEICE),  accepted for publication.

 

[2] D. Stojan, B. Vasic, J. M. Wang, and C. Charalambous, “Information theoretic modeling and analysis for global interconnects with process variations,” IEEE Trans. on Very Large Scale Integrated Systems,  accepted for publication.

 

[3]  A. Mitev, M. Marefat, D. Ma and J. M. Wang, “Parameter reduction for variability analysis by SIR method,” (Invited), IEE Proceedings for Circuits, Devices and Systems, accepted for publication.

 

[4] V. Agarwal, J. Sun and J. M. Wang, “Delay uncertainty reduction by gate-interconnect splitting,” IEEE Trans. on Circuit and System II, accepted for publication.

 

[5] A. Mitev, M. Marefat, D. Ma, and J. M. Wang, “Principle hessian direction based parameter reduction for interconnect networks with process variation,” IEEE Trans. on Very Large Scale Integrated Systems, accepted for publication.

 

[6] O. Hafiz, J. M. Wang, “LFT based parametric interconnect Modeling,” Transaction of the Institute of Electronics, Information and Communication Engineers (IEICE), Vol. E92-A, No. 4, Apr. 2009.

 

[7] Li Xin, Janet M.Wang, Zhang Ying, Tang Wei-qing, Wu Hui-zhong, “Spectral Method
for Analysis of Crosstalk of Non2uniform RLC Interconnect s in the Presence
of Process Variations”, Journal of Electronics, Vol. 37, no. 2, pp. 398-403, Feb. 2009.

 

[8] J. M. Wang, Y. Cao, M. Chen, J. Sun, A. Mitev, and K. Potluri, “Capturing device mismatch in analog and mixed-signal design,” Invited Paper, IEEE Circuits and Systems Magazine, Vol. 8, No. 4, pp. 37-44, 2008.

 

[9] J. Sun, J. Li, D. Ma and J. M. Wang, “Chebyshev affine arithmetic based parametric yield prediction under limited descriptions of uncertainty,” IEEE Trans. on Computer-Aided Design, Vol. 27, No. 10, pp. 1852-1866, Oct. 2008.

 

[10] D. Ma, J. M. Wang, and M. Song, "Adaptive on-chip power supply with robust one-cycle control technique,” IEEE Transaction on VLSI, Vol. 16, No. 9, pp. 1240-1243, September 2008.

 

[11] U. Padmanabhan, J. M. Wang and J. Hu, “Robust clock tree routing in the presence of process variations,” IEEE Trans. on Computer-Aided Design, Vol. 29, No. 8, pp. 1385-1397, August 2008.

 

[12] K. Muchherla, P. Chen, D. Ma and J. M. Wang, “A Non-iterative equivalent waveform model for timing analysis in the presence of crosstalk,” ACM Trans. on Design and Automation of Electronic Systems, Vol. 13, Issue 2, No. 25, April 2008.

 

[13] J. M. Wang, B. Sukhwani,  U. Padmanabhan, D. Ma and K. Singha, “Simulation  and design of nanocircuits with resonant tunneling devices,” IEEE Trans. on Circuits and Systems-I, Vol. 54, No. 6, pp. 1293-1304, June 2007.

 

[14] J. M. Wang, J. Li, S. Yanamanamanda, K. Vakati, and K. Muchherla, “Modeling the driver load in the presence of process variations,”  IEEE Trans. on Computer-Aided Design, Vol. 25,  No. 10, pp. 2264 - 2275, October 2006.

 

[15] S. Vrudhula, J. M. Wang, and P. Ghanta, “Hermite polynomial based interconnect analysis in the presence of process variations,” IEEE Trans. on Computer-Aided Design, Vol. 25, No. 10, pp. 2001-2011, October 2006.

 

[16] Y. Zhang, J. M. Wang, L. Xiao, and H. Wu, “Stochastic modeling for transmission lines and numerical experiment analysis for transient simulation,” Journal of Electronics and Information Technology, Vol. 28, No. 8, pp. 1516 – 1520, August 2006.   

 

[17] J. M. Wang, P. Chen, K. Muchherla, S. Yanamanamanda and O. Hafiz, “A non-iterative continuous model for switching window computation with crosstalk noise,” Invited to The Journal of Microelectronic Engineering Special Issue on VLSI Design and Test, Elsevier, Vol 3. 2006.

 

[18] Y. Lee, Y. Cao, T. Chen, J. M. Wang and C. C.-P Chen,  “ HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery,” IEEE Trans. on Computer-Aided Design, Vol. 24, No. 6, pp. 797 – 806, June 2005.

 

[19] L. K. Vakati,  K. K. Muchherla, and J. M. Wang “A New three-piece driver model with RLC interconnect load,” Transaction of the Institute of Electronics, Information and Communication Engineers (IEICE), Vol. E88.A,  No. 8, pp. 2206 – 2215, August 2005.

 

[20]* J. M. Wang, C. Chu, Q. Yu and E. S. Kuh,  “On Projection-based Algorithms for Model-order Reduction of Interconnects,” IEEE Trans. on Circuits and Systems I, Vol. 49, No. 11,  pp. 1563 – 1585, November 2002.

 

[21]* Q. Yu, J. M. Wang and E. S. Kuh, “Passive multipoint moment matching model order reduction algorithm on multiport distributed interconnect networks,” IEEE Trans. on Circuits and Systems I, Vol. 46, No. 1, pp. 140 – 160, January 1999.

 

Conferences/Symposia:

 

 

[1]  T. Yoshimura, T. Hosono, J. Li and J. M. Wang, “A New Generation Static Statistical Timing Analysis (SSTA) Based Design Flow for 40nm and 28nm CMOS Technology,” accepted for publication in IEEE Design Automation Conference (DAC), June 2010.

 

[2]  J. Sun, R. Lysecky, K. Shankar, A. Kodi, A. Louri, J. M. Wang, “Workload Capacity Considering NBTI Degradation in Multi-core Systems,”  accepted for publication in IEEE Asia and South Pacific Design Automation Conference (ASPDAC), January 2010.

 

[3] J. Sun, J. M. Wang, “Robust Gate Sizing by Uncertainty Second Order Cone,” accepted for publication in International Symposium & Exhibits on Quality Electronic Design (ISQED), Best Paper Award.

 

[4]  A. Kodi, A. Sarathy, A. Louri, and J. M. Wang, “Adaptive Inter-router Links for Low-Power, Area-Efficient and Reliable Network-on-Chip (NoC) Architectures,”  IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 1-6, January 2009. Best Paper Award Candidate

 

[5] A. Kodi, A.Louri, and J. M. Wang, “Energy-Efficient Router Buffers with Bypassing for Network-On-Chips (NoCs),”  International Symposium & Exhibits on Quality Electronic Design (ISQED), pp. 826 - 832, March 2009.

 

[6] J. Sun, A. Kodi, A. Louri and J. M. Wang, “NBTI Aware Workload Balancing in Multi-core System,”  accepted for publication in International Symposium & Exhibits on Quality Electronic Design (ISQED), pp. 833 - 838, March 2009.

 

[7] J. Chen, J. Sun and J. M. Wang, “Robust Interconnect Communication Capacity Algorithm by Geometric Programming,” International Symposium on Physical Design (ISPD), pp. 19-26, March 2009.

[8] R. Raghave, A. Kodi, A. Louri, and J. M. Wang, “High Speed Inter-Router Link Design for Networks On Chip (NoC) Architectures,” Austin Conference on Circuit and Systems, October, 2009

[9] P. Green, J. M. Wang, “A New NBTI Sensor for Chip Multi-Processor (CMP) Monitoring Applications,” Austin Conference on Circuit and Systems, October, 2009.

 

[10] D. Nguyen, A. Baysal, H. Cormican, T. Kerr, C. Wiswall, R. Lohrenz, D. Ma and J. M. Wang, “A mammography imaging hybrid pixel sensor test chip with low noise CMOS readout IC on fully depleted sillicon-on-insulator design trade off study,” Symposium on Radiation Measurements and Applications (SORMA), June 2008.

 

[11] D. Ganesan, A. Mitev, Y. Cao and J. M. Wang, “Finite-point gate model for fast timing and power analysis,” International Symposium on Quality Electronic Design, pp. 657-662, March 2008. 

 

[12] S. Varadan, J. M. Wang, J. Hu , “Handling partial correlations in yield prediction,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 543 - 548, January 2008

 

[13] J. Sun, Y. Huang, J. Li, and Janet M. Wang, “Chebyshev affine arithmetic based parametric yield prediction under limited descriptions of uncertainty,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 531 - 536, January 2008

 

[14] A. Mitev, M. Marefat, D. Ma and J. M. Wang, “Principle hessian direction based parameter reduction with process variation,” nominated as best paper candidate, IEEE/ACM International Conference on Computer-Aided Design (ICCAD),  pp. 632 – 637, November 2007. (Best Paper Award Candidate)

 

[15]  A. Mitev, D. Canesan, D. Shammgasundaram, Y. Cao and J. M. Wang, “A robust finite-point based gate model considering process variations,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD),  pp. 692 – 697, November 2007.

 

[16]  D. Nguyen, MA. Baysal, E. Toker and J. M. Wang, “Design and initial performance evaluation of a full field digital mammography upgrade cassette,” Proceedings of SPIE, September 2007.

 

[17] A. Mitev, M. Marefact, D. Ma, and J. M. Wang, “Parameter reduction for variability analysis by slice inverse regression (SIR) method,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 468 – 473, January 2007.

 

[18] V. Agarwal, J. Sun, A. Mitev, and J. M. Wang, “Delay uncertainty reduction by interconnect and gate splitting,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 690 – 695, January 2007.

 

[19] D. Ma, J. M. Wang,  P. Vazquaz “Adaptive on-chip power supply with robust one-cycle control technique,” IEEE/ACM International Symposium on Low Power Electronics (ISLPED), pp. 394 – 399, Germany 2006.

 

[20]  U. Padmanabhan, J. M. Wang and J. Hu, “Statistical clock tree routing for robustness to process variations,” ACM International Symposium of Physical Design (ISPD), pp. 149 – 156, April 2006.

 

[21] N. Kankani, V. Agarwal and J. M. Wang, “A probabilistic analysis of pipelined global interconnect under process variations,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 724 – 729, January 2006.

 

[22] V. Agarwal and J. M. Wang, “Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA),” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 718 – 723, January 2006.

 

[23] J. M. Wang, B. Srinvas, D. Ma, C. C-P. Chen and J. Li, “System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS),” IEEE/ACM International Conference on Computer-Aided Design (ICCAD),  pp. 728 – 735, November 2005.

 

[24] R.  Jiang, W. Fu, J. M. Wang, V. Lin and C. C-P. Chen, “Efficient statistical capacitance  variability modeling with orthogonal principle factor analysis,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 683 – 690,   November 2005.

 

[25] D. Ma, J. M. Wang, M. N. Somasundaram and Z. Hu, “design and optimization on dynamic power system for self- powered integrated wireless sensing nodes,” International  Symposium on Low Power Electronics and Design (ISLPED),  pp. 303 – 306, August 2005.

 

[26] J. M. Wang, A. Mitev and N. Kankani, “Collocation method based RC/RLC extraction with process variation,” Progress in Electromagnetic Research Symposium (PIERS), abstract, Hangzhou, China, August 2005.

 

[27] Y. Zhang, J. M. Wang, L. Xiao and H. Wu, “Adaptive difference method and singular treatment approach for fast parameters extraction of interconnects in MEI system,” Proc. International Conference on Communications, Circuits and Systems(ICCCS), Vol. 2,  pp. 1196 – 1200, May 2005.

 

[28] B. Sukhwani and J. M. Wang, “A stepwise constant conductance approach for simulating resonant tunneling diodes,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2518 – 2521, Kobe, Japan, May 2005.

 

[29] K. K. Muchherla, P. Chen and J. M. Wang, “A non-iterative equivalent waveform model for timing analysis in presence of crosstalk,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2465 – 2468, Kobe, Japan, May 2005.

 

[30] C. Talarico, B.S. Pillilli, K.L Vakati and J.M. Wang, “Early assessment of leakage power for  system level design,” International Symposium of Quality Design (ISQED), pp. 133 – 136, March 2005. (Best Paper Award Candidate) 

 

[31] B. Sukhwarni, U. Padmanabhan, and J. M. Wang, “Nano-Sim: a step wise equivalent conductance based statistical simulator for nanotechnology circuit design,” Proc. Design, Automation and Test in Europe (DATE), pp. 133 – 136,  March  2005.

 

[32] P. Ghanta, S. Vrudhula, R. Panda, and J.M. Wang, “Stochastic power grid analysis considering process variations,” Proc. Design, Automation and Test in Europe (DATE), pp. 964 – 969, March 2005.

 

 

[33] V. Agarwal, N. Kankani, R. Rao, S. Bhardwaj, and J.M. Wang, “An efficient combinationality check techniques for the synthesis of cyclic combinational circuits,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 212 – 215, January 2005.

 

[34] P. Saxena, L.N. Kumar, G. Hans, and J.M. Wang, “A perturbation-aware noise convergence methodology for high performance microprocessors,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 717 – 722, January 2005.

 

[35] J. M. Wang, P.Ghanta, and S. Vrudhula, “stochastic analysis of interconnect networks in  the presence of process variations,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 880 – 887, November 2004.

 

[36] J. M. Wang, O. A. Hafiz and J. Li, “A Linear fractional transform (LFT) based model  for interconnect parametric uncertainty,”  Proc. ACM/IEEE Design Automation Conference (DAC), pp. 375 – 380, June 2004.

 

[37]  S. Raj, S. Vrudhula and J. M. Wang, “A methodology to improve timing yield in the presence of process variations,” Proc. ACM/IEEE Design Automation Conference (DAC), pp. 448 – 453, June 2004.

 

 

[38] L.K.Vakati and J. M. Wang, “A new three-ramp driver model with RLC interconnect load,”   IEEE International Symposium on Circuits and Systems (ISCAS), pp. 269 – 272, May 2004.

 

[39] O.Hafiz, J.M.Wang, “A new non-iterative model for switching window computation with crosstalk noise,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 497 – 500, May 2004.

 

[40] J.M.Wang and O.Hafiz, “predicting interconnect uncertainty with a new robust model order reduction method,” International Symposium of Quality Design (ISQED), pp. 363 – 368, March 2004.

 

[41] J.M.Wang, K.K Muchherla,  and J. G. Kumar, “A clustering based area I/O planning for flip-chip technology,” International Symposium of Quality Design (ISQED), pp. 196 – 201, March 2004.

 

[42] S. Raj, S. Vrudhula and J.M.Wang, “Statistical gate sizing to increase timing yield,” ACM/IEEE International Workshop on Timing Issues (TAU), February 2004.

 

[43] L.K.Vakati and J. M. Wang, “A new multi-ramp driver model with RLC interconnect load,” ACM  International Symposium on Physical Design (ISPD), pp. 170 – 175, April 2004.

 

[44] J. M. Wang, O. Hafiz and P. Chen, “A non-iterative model for switching window computation with crosstalk noise,”  IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 847 – 852, January 2004.

 

[45] J.M. Wang, P. Chen and O. Hafiz, “Switching windows computation in the presence of  crosstalk noise,” Proc. International Conference on VLSI, Las Vegas, pp. 114 – 118, June 2003.     

[46] J. M. Wang, P. Chen and O. Hafiz, “a new continuous switching window computation with crosstalk noise,” 16th Symposium on Integrated Circuits and Systems Design, pp. 261 – 266, September 2003.

 

[47] Q. Yu, J. M. Wang and E.S. Kuh, “Passive model order reduction algorithm based on Chebyshev expansion impulse response of interconnect networks,” Proc. ACM/IEEE Design Automation Conference (DAC),  pp. 520 – 525, Los Angeles, California, June 2000.

 

[48] J. M. Wang and T. V. Nguyen, “Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources,” Proc. ACM/IEEE Design Automation Conference (DAC),  pp. 247-252, June 2000.

 

[49] J. M. Wang, E. S. Kuh and Q. Yu, “The Chebyshev expansion based reduced order model for distributed interconnect networks,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 370 – 375,  November 1999.

 

[50]  J. M. Wang and E.S. Kuh, “Recent development in interconnect modeling,” European Conference on Circuit Theory and Design (ECCTD), pp100-140, 1999.

 

[51] J. M. Wang, Q. Yu and E. S. Kuh, “Coupled noise estimation for distributed RC Interconnect Model,” Proc. Design, Automation and Test in Europe (DATE), pp. 664 – 668, March 1999.

   

[52]  Q. Yu, J.M. Wang and E.S. Kuh, “Multipoint multiport algorithm for passive reduced-order model of interconnect networks,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 74 – 77, June 1998.

 

[53]  Q. Yu, J. M. Wang and E. S. Kuh, “Multipoint moment matching model for multiport distributed interconnect networks,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 85 – 91, November 1998.

 

[54] J. Mao, J. M. Wang and E.S. Kuh, “simulation and sensitivity analysis of transmission line circuits by the characteristics method,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 556 – 562, November 1996.

 

[55] E.S.  Kuh, J. F. Mao, and J. M. Wang, “Interconnect simulation based on passivity and method of characteristics,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 449 – 457, November 1996.