Shih-Lien Lu, Microarchitecture Research, Intel Labs
Nam Sung Kim, Circuit Research, Intel Labs
Steven Hsu, Circuit Research, Intel Labs

More and more devices on a microprocessor are devoted to memory arrays nowadays. For example, more than 50% of the devices among the 3 million+ transistors on the first generation Pentium™ were used for implementing cache, table, register files, etc. However, these memory arrays are quite different in circuit topology and have different characteristics due to their requirements. Some are based on differential small signals, while others are single ended full swing. This tutorial intends to extract out general technology and circuit information for microarchitects and architects. The intention is to provide a general understanding of the circuit design, so correct tradeoffs can be made at the architectural level.

A list of topics to be covered and some of their related bibliography:

• SRAM arrays and organization - decoder, word-line, local and global bit-line, column muxes, sub-array
• Size, performance, Vcc-min, and yield tradeoffs of SRAM arrays
• SRAM circuit-level leakage reduction techniques
• Pitfalls in existing cache performance/power estimation tools
• Register files - multiple read/write ports, power reduction, leakage control
• Special arrays - content addressable memory
• Future trends challenges of memory arrays on microprocessors

Duration: 1/2 day