General Chair
Ahmed Louri, Univ. of Arizona
Mazin Yousif, Intel Corp.

Program Chair
Trevor Mudge, Univ. of Michigan

Program Committee
Murali Annavaram, Intel Corp.
Iris Bahar, Brown Univ.
David Brooks, Harvard Univ.
Doug Burger, Univ. of Texas
Brad Calder, UCSD and Microsoft
Chaitali Chakrabarti, Arizona State Univ.
Tom Conte, North Carolina State Univ.
Chita Das, Penn State Univ.
Lieven Eeckhout, Ghent Univ.
Krisztian Flautner, ARM Ltd.
Kim Hazelwood, Univ. of Virginia
Paolo Ienne, EPFL
Bruce Jacob, Univ. of Maryland
Dave Kaeli, Northeastern Univ.
Nam Sung Kim, Intel Corp.
Hsien-Hsin Lee, Georgia Tech.
Charles Lefurgy, IBM Austin
Scott Mahlke, Univ. of Michigan
Bill Mangione-Smith, Intellectual Ventures
Rami Melhem, Univ. of Pittsburgh
David Nagle, Panasas Corp.
Walid Najjar, UC Riverside
Vijaykrishnan Narayanan, Penn State Univ.
Mike O'Boyle, Univ. of Edinburgh
Kunle Olukotun, Stanford Univ.
Krishna Palem, Georgia Tech.
Sanjay Patel, Univ. of Illinois
Yale Patt, Univ. of Texas
Li-Shiuan Peh, Princeton Univ.
Milos Prvulovic, Georgia Tech.
Tom Puzak, IBM Watson
Olivier Temam, INRIA
Nigel Topham, Univ. of Edinburgh
Gary Tyson, Florida State Univ.
Richard Uhlig, Intel Corp.
Mateo Valero, UPC, Barcelona
Zhiwei Xu, Inst. of Comp. Tech., CAS

Publicity Chair
Avinash Kodi, Univ. of Arizona

Publications Chair
Greg Byrd, North Carolina State Univ.

Workshop/Tutorial Chair
Ricardo Bianchini, Rutgers Univ.

Local Arrangements Chair
Kshitij Doshi, Intel Corp.

Web Chair
Roman Lysecky, Univ. of Arizona

Steering Committee
Laxmi Bhuyan, UC Riverside
Yale Patt, Univ. of Texas
Josep Torrellas, Univ. of Illinois
Chita Das, Penn State Univ.
Craig Chase, Univ. of Texas

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to:

  • Processor architectures
  • Cache and memory systems
  • Parallel computer architectures
  • Impact of technology on architecture
  • Power-efficient architectures and techniques
  • High-availability architectures
  • High-performance I/O systems
  • Embedded and reconfigurable architectures
  • Interconnect and network interface architectures
  • Network processor architectures
  • Innovative hardware/software trade-offs
  • Impact of compilers on architecture
  • Performance evaluation of real machines
  • Optical and other emerging technologies

Authors should submit an abstract before July 7, 2006, midnight EST. They should submit the full version of the paper before July 14, 2006, 11:59 PM EDT. No extensions will be granted. The full version of the paper should be a PDF file that does not exceed 6,000 words according to the instructions in Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. Please contact the program chair at for any submission issues. Submitted papers must not be under review in any other conference or journal. Papers should be submitted for blind review, and will be evaluated based on their novelty, fundamental insights, relevance, presentation and potential for long-term contribution. New-idea papers are encouraged. Please indicate whether the paper is a student paper for best student paper nominations. The student will be required to attend the conference and present the paper to receive the award.

Accepted papers will be published in the conference proceedings to be distributed to conference attendees. Papers will also be uploaded to IEEE Xplore

Important Dates

  • Abstract submission: July 7, 2006, midnight EST (firm deadline)
  • Paper submission: July 14, 2006, 11:59 PM EDT (firm deadline)
  • Workshop & tutorial proposals due: August 13, 2006, midnight EST
  • Notification of paper outcome: September 25, 2006