Floating Point Partitioning

Hardware/Software Partitioning of Floating-Point Applications

While hardware/software partitioning has been shown to provide significant performance gains, most hardware/software partitioning approaches are limited to partitioning computational kernels utilizing integers or fixed point implementations. Software developers often initially develop an application using built-in floating point representations and later convert the application to a fixed point representation a potentially time consuming process. We have developed an initial hardware/software partitioning approach for floating point applications that eliminates the need for developers to rewrite software applications for fixed point implementations. Instead, this approach incorporates efficient, configurable floating point to fixed point and fixed point to floating point hardware converters at the boundary between the hardware coprocessors and memory. This effectively separates the system into a floating point domain consisting of the microprocessor and memory subsystem and a fixed point computing domain consisting of the partitioned hardware coprocessors, thereby providing an efficient and rapid method for implementing fixed point hardware coprocessors. Our hardware/software partitioning approach for a floating point application provides application speedups of 4.3X on average without requiring any designer effort to re-implement software with a fixed point representation.

Arizona Float <-> Fixed Hardware Library (AFFHL)

The Arizona Float <-> Fixed Hardware Library (AFFHL) is a highly configurable set of floating point to fixed point (Float2Fixed) and fixed point to floating point (Fixed2Float) hardware converters implemented in Verilog. These converters have been successfully utilized within our hardware/software partitioning of floating point applications to fixed point coprocessors.

While we have made every effort to ensure the correctness of these designs, we cannot make any guarantees as to complete correctness of the provided designs. However, we have included an extensive of set testbenches utilized to test our designs. If you have any quetions or would like to report any bugs in the design, please email esdl@ece.arizona.edu.

On a final note, Merriam-Webster defines awful as:

  1. inspiring awe
  2. filled with awe:
  3. extremely disagreeable or objectionable
  4. exceedingly great

We hope you find AFFHL to any of those except #3.

Current Release (January 16, 2014): AFFHL 011614

Previous Releases

  1. July 18, 2010: AFFHL 071810
  2. January 16, 2009: AFFHL 011609


Publications

  1. V. K. Nileshwar, R. Lysecky. SNR Analysis Approach for Hardware/Software Partitioning using Dynamically Adaptable Fixed Point Representation, ACM Great Lakes Symposium on VLSI (GLVIS), 2012.
  2. L. Saldanha, R. Lysecky. Float-to-Fixed and Fixed-to-Float Hardware Converters for Rapid Hardware/Software Partitioning of Floating Point Software Applications to Static and Dynamic Fixed Point Coprocessors. Journal on Design Automation of Embedded Systems, Vol. 13, No. 3, pp. 139-157, 2009. PDF
  3. L. Saldanha, R. Lysecky. Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Point Coprocessor Circuits. International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), 2008.PDF PPT
    Received Best Paper Award


Acknowledgments

This research was supported in part by the National Science Foundation (CNS-0844565).

* Research Projects

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