OLGIERD A. PALUSINSKI

Department of Electrical and Computer Engineering,

The University of Arizona, Tucson, AZ 85721,

Ph.: (520) 621-4928, Fax: (520) 621-8076,

E-mail: palusinski@ece.arizona.edu,

http://www.ece.arizona.edu/~palusin

EDUCATION

1960 MSEE, Technical University of Silesia, Poland

1966 Ph.D., Summa cum Laude, Technical University of Silesia, Poland

1968 Docteur de l'Université, Technical University of Lille, Lille, France.

ACADEMIC EXPERIENCE

1990-Date - Professor of Electrical Engineering, University of Arizona, Tucson, USA.

1976-1990 - Visiting, Associate Professor of Electrical Engineering, University of Arizona.

1966-1976 - Assistant, Associate Professor (since 1970), Department of Control and Information Engineering, Technical University of Silesia, Gliwice, Poland.

RECENT SABBATICAL LEAVES - INDUSTRY COOPERATION

1999 - Wireless Infrastructure Systems Group, Motorola, Inc. - Senior Consultant.

1998 - summer, Wireless Infrastructure Systems Group, Motorola, Inc. - Senior Consultant.

1997 April-August, Univ. of Karlsruhe, research on packaging, mixed-signal circuits, and Field Programmable Analog Arrays (FPAA) technology sponsored by German Science Foundation fellowship.

1996 - summer - Logic/Analog Technology Group, Motorola Inc. - Senior Consultant (FPAA).

1994 -1995 Advanced Packaging Development Center (APDC), Motorola Inc. - Senior Consultant, full time position offered, accepted: - 1/2 time in Spring 94 and Fall 94, full time in Summer 94 and 95.

1993 APDC, Motorola - 3 months (summer), full time.

1991-1992 University of Karlsruhe, Germany ( 5 months-91/92), and APDC, Motorola Inc., Phoenix, Arizona (7 months - 92, full time).

RESEARCH INTERESTS

Signal integrity in circuits and systems, phase noise in oscillators, interconnect modeling and simulation, behavioral modeling of signal converters for wireless communication, dynamically reconfigurable mixed-signal circuits, electronic packaging engineering, simulation techniques for RF circuits and packages, multi-criteria optimization in mixed-signal circuits.

RESEARCH EXPERIENCE

Participation in several sponsored research projects related to the areas listed above as Principal Investigator. Sabbatical stays at Advanced Packaging Development Center, Logic Analog Technology, and Wireless Infrastructure Systems Groups of Motorola Inc. Consulting for Motorola in the area of Field Programmable Analog Arrays and converters for wireless applications. Over forty publications in refereed journals and in addition numerous publications in conference proceedings.

CURRENT RESEARCH PROJECTS – at the Center for Low Power Electronics

Power Minimization via Dynamic Reconfiguration and Mixed-signal Technology.

Modeling and Simulation of Signal Converters for Wireless Communication.

A Development System for Rapid Prototyping of Dynamically Reconfigurable Mixed-signal Low Power Systems – involving Field Programmable Gate and Analog Arrays.

Spectral method for simulation of RF circuits.

United States Patents

Self Adjusting CMOS Transmission Line Driver, Patent Number: 5,296,756 (with 2 co-inventors).

Control of track/compute mode in FPAA – pending.

RECENT PUBLICATIONS

1. Lee, D. and O. A. Palusinski, 1994, “Adaptation of SPICE3 to Simulation of Lossy, Multiple-Coupled Transmission Lines”, IEEE Trans. on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol. 17, No. 2, May 1994, pp. 126-123.

2. Palusinski O. A. and F. Szidarovszky, 1994, “A Chebyshev Expansion Method for Solving of Nonlinear Circuit Equations”, Applied Mathematics and Computation, Vol. 60, 1994, pp. 299-310.

3. Szidarovszky, F. and O. A. Palusinski, 1995, “An Inverse Method to Determine Parasitics of Power Interconnections in High Speed Electronics”, Applied Mathematics and Computation, Elsevier Science Inc., Dec. 1995.

4. Vakanas, L. P., A. C. Cangellaris, O. A. Palusinski, 1994, “Scattering Parameters-Based Simulation of Transients in Lossy, Non-linearly Terminated Packaging Interconnections”, IEEE Trans. On Components, Packaging, and Manufacturing Technology - Part B, vol. 17, No. 4, Nov. 1994, pp. 472-479.

5. Reiss, K. and O. A. Palusinski, 1996, “Procedure for Direct Calculation of Characteristic Admittance Matrix of Coupled Transmission Lines”, IEEE Trans. on Microwave Theory and Techniques, vol. 44, No. 1, January 1996, pp. 152-154.

6. Tokat, Y., O. A. Palusinski, F. Szidarovszky, 1998, “Multi-criteria decision making in design of printed wire boards”, IEEE Trans. on Advanced Packaging, vol. 21, No.1, Feb. 1998.

7. Znamirowski, L. and O. A. Palusinski, 1998, “Analysis of error in measuring coupling capacitance in multi-conductor transmission lines”, IEEE Proceedings - Science, Meas. and Techn. March 1998.

8. Palusinski, O. A., D. M. Gettman, D. Anderson, H. Anderson, C. Marcjan, 1998, “Filtering Application of Field Programmable Analog Arrays”, Journal of Circuits, Systems and Computers, vol. 8, No. 3 1998, pp. 337-353.

9. Palusinski, O. A., C. K. Lee, B. S. Seol, Y. You, F. Szidarovszky, 1998, “Mathematical basis of a system supporting interconnection design”, Southwest Journal of Pure and Appl. Math., 1998.

10. Palusinski, O. A., K. Reiss, and F. Szidarovszky, 1998, “Algorithms Supporting Driver/receiver Design for Multi-conductor Interconnects”, Symp. on Signal Prop. Proc. Kluwer Publ., Boston, 1998, pp. 59 - 69.

11. Szidarovszky, F. and O. A. Palusinski, 1999, “Clarification of A Decoupling Method for Multiconductor Transmission Lines”, IEEE Trans. on Microwave Theory and Techniques, vol. 47, No. 5, May 1999.

12. You, Y., O. A. Palusinski and F. Szidarovszky, 1999, “New Matrix Algorithm for Calculating Diagonally Matched Impedance of Packaging Interconnecting Lines” , IEEE Trans. on Microwave Theory and Techniques, vol. 47, No. 6, June 1999.

13. Stehr, G., F. Szidarovszky, O. A. Palusinski, D. Anderson, 1999, “Performance Optimization of Current-steering D/A Converters”, Southwest Journal of Pure and Appl. Math., 1999.

14. Huang, W., O. A. Palusinski, D. L. Dietrich, 2000, “Effect of Randomness of Cu-Sn Intermetallic Compound Layer Thickness on Reliability of Surface Mount Solder Joints”, IEEE Trans. on Advanced Packaging, vol. 23, No.2, May 2000.

ENCYCLOPEDIA OF ELECTRICAL AND ELECTRONICS ENGINEERING - John Wiley & Sons, 1998, O. A. Palusinski, “Electrical Simulation of Semiconductor Packages and Systems” - article 2111.