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Research Interests:
My research program is driven by the adaptive hardware architecture demand of the space, consumer, medical, defense, and security markets, and the computing demand of the nation's scientific community. My objective is to advance the fields of reconfigurable computing and high performance scientific computing, and translate the emerging knowledge arising from focused research efforts into innovative technologies.

Reconfigurable Computing:
If computing is to become ubiquitous throughout society, it must be reliable. The demand from many fields, including medicine, aerospace, military/defense and consumer products for a wide range of processors (e.g., application specific, general purpose, server based) has necessitated the creation of an environment of "no doubt" with fault-tolerant computing architectures. Field Programmable Gate Array (FPGA) technology allows the end-user to reconfigure the hardware with the desired functionality. I am interested in FPGAs for developing a system in which individual subsystems automatically respond to anomalies with self-healing action, and coordinate their actions for a broader range of objectives based on fault detection, isolation and recovery through dynamic and partial reconfiguration capabilities.

Shrinking process technologies have enabled the development of SoC architectures, which integrate microprocessor(s) with reconfigurable fabrics, particularly through field programmable gate array (FPGA) technologies, in an effort to meet increasing energy efficiency and performance demands. As the spectrum of FPGA applications is rapidly growing, the FPGA community is facing a number of interesting challenges from three major fronts - application engineering, FPGA architecture design, and CAD tool development.

  • From the application engineering perspective, whenever a design undergoes a change, the design has to be re-synthesized for the target device, which increases the overall design time.
  • From architecture designers' perspective, with increasing heterogeneity in the FPGA based systems, architects face the challenge of conducting large scale and time consuming CAD experiments for identifying the most suitable hardware configuration for their target application.
  • Last but not least, CAD tools for FPGAs are becoming slower with the increase in the device and design size.
Application, architecture, and CAD tool developers need a tool that is fast and "good enough" to predict the post routing impact of the change they plan to make without having to go through the actual physical optimizations and implementation tools. In the reconfigurable computing lab, we work on design and development of tools and models to enable rapid performance estimation of a given application on a hypothetical reconfigurable architecture by taking complete logic and routing architecture parameters into account. Our goal is to enable hardware architects and application developers to work in a consolidated design environment, where:
  • Application engineers can quickly evaluate design changes to gauge the quality of their partitioning choice without having to run the CAD tools, as well as predict how these changes affect the post-routing scenario of the design.
  • Architects are able to explore all the combinations of the architecture parameters for a given set of benchmark designs and quickly evaluate the impact of each architecture choice on quality metrics such as routability, power (energy) and timing.
  • CAD tool developers can similarly integrate the prediction methodology within their optimization algorithms to make informed decisions based on the predicted post-routing circuit characteristics, thereby directing their algorithms towards timing closure, routability and power optimization much faster than those currently in use.

High Performance Scientific Computing:
The ingenuity of parallelizing an algorithm comes into play when trying to balance the usage of computation and memory resources on the target hardware, and manage the memory all the way down to a byte-by-byte basis. My lab has contributed to the scientific computing domain with: 1) design and development of scalable and novel approach to sequence alignment problem using the graphics processing unit (GPU) technology; 2) development of novel methods to accelerate T-Cell Receptor (TCR) synthesis for studying the immune systems of complex organisms; 3) completion of the first study on joining Variable, Diverse, and Joining (VDJ) gene segments using GPU to determine all possible ways (several trillions of sequences) in which proteins can be encoded to match antigens from viruses, cancers, and other diseases; 4) developing high performance algorithms for rapid identification of phenotype to genotype linkage with GPU based HPC systems; and 5) building a library of next-generation sequencing and error correction algorithms for improving assembly quality and detecting gene-gene interactions with large scale data sets.

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